CommILP: Synthesizing Communication Infrastructure for Domain Computing Platforms

Domain-specific accelerator-rich platforms are promising for high-throughput, low-power edge systems. Prior domain design-space exploration (Domain-DSE) methods [1] efficiently allocate processing elements (PEs) and bind applications, but largely assume simplified, centralized communication within the hardware tile, which limits scalability and wastes resources. Novel research work is needed that takes advantage of designtime known communication patterns to synthesize custom intratile interconnects that minimize area and energy while preserving application throughput. This paper introduces CommILP for synthesizing intra-tile communication infrastructure given a platform allocation and PE-to-PE communication graphs for multiple applications. CommILP instantiates Communication Elements (CEs), determines a minimal interconnect topology, and assigns routing paths for each app and connection. It guarantees that application throughput is preserved while minimizing area and energy. CommILP introduces a hierarchical ILP formulation across platform, application, and hop-stack levels, and supports both App-Level and Domain-Aggregated modeling modes to balance solution quality and runtime. Evaluated on ASIC and FPGA backends using both real (OpenVX-40) and synthetic (RNDComm-100) domains, CommILP achieves up to 69.4% area and 73% energy savings over centralized baselines, while remaining scalable to over 100 applications. It complements existing platform DSE tools by bridging the gap between computation binding and hardware-efficient communication synthesis.