Synthesis of CFET Standard Cells Utilizing Backside Interconnects Towards Improving Pin Accessibility

This work addresses the problem of automatic synthesis of CFET (Complementary FET) standard cells with maximal use of the backside metals, so that the pin accessibility on the frontside should be maximally improved. Specifically, we propose optimal solutions to the two subproblems: (1) pruning partial solutions in the transistor placement phase and (2) in-cell routing. For (1), we employ a graph-based exhaustive exploration with fast front/backside metal connectivity checking for pruning while for (2), we develop a satisfiability modulo theory (SMT) based formulation with a maximal use of backside metals as the utmost priority. Through experiments, it is shown that CFET cells generated by our method use on average 24.4% less frontside metals over that of the conventional CFET cells while significantly reducing runtime by employing pruning technique of using our fast metal accessibility checking. Furthermore, when chip placement and routing are performed using our CFET cells, we are able to produce final implementations with on average $\mathbf{6 7. 5 \%}$ less DRVs and $\mathbf{2. 1 \%}$ less wirelength over that produced by using conventional CFET cells.