CNN-Assisted Low-Power Clock Tree Synthesis for 3D ICs

In this work, a convolutional neural network (CNN)-assisted low-power clock topology generation method for 3D clock tree synthesis (CTS) is proposed. Our approach considers both local and global costs in each merging step to prevent getting stuck in local optima. To explore the trade-off between local and global costs, we use CNN to set two important weighting factors to obtain an optimized clock tree that reduces power consumption. Compared with the conventional NNG-based method, experimental results on ISPD09 benchmarks show that our approach can reduce wirelength by 5.83% and power consumption by 4.73% on average. We also demonstrate the transferability of our method on larger-scale ISPD10 benchmarks.