Topological Optimization-Based Layer Assignment Method for Fan-Out Wafer-Level Packaging

Fan-Out Wafer-Level Packaging (FOWLP) achieves heterogeneous chip integration through redistribution layers (RDLs). However, the rapid increase in interconnect density has significantly heightened the topological complexity of net crossings. In light of manufacturing cost constraints and limited routing resources, reducing topological crossings among nets through layer assignment becomes critically important. Unlike existing RDL layer assignment methods that rely on fixed access point circular models, our approach introduces a flexible access point strategy to minimize topological conflicts among nets, thereby reducing the total number of routing layers. The proposed method includes the following key techniques: (1) a multi-directional projection circular (MDPC) model with support for flexible access points to expand the solution space; (2) a global topology optimization strategy based on flexible access points to significantly reduce net crossings; and (3) a wirelength-driven access point allocation algorithm aimed at minimizing total wirelength. Experimental results show that, compared with the fixed access point-based method and the limited flexible access points-based method, the proposed algorithm reduces the number of routing layers by 36.5% and 17.9%, respectively, when the number of layers is not constrained, and increases the number of assigned nets by 19% and 5%, respectively, under fixed-layer constraints.