Effective RC Reduction via Graph Sparsification for Accurate Post-Simulation of Mixed-Signal ICs

Asia and South Pacific Design Automation Conference (ASP-DAC) 2026

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Authors: Yibin Zhang, Z. A. Liu, Shan Shen, Chao Hu, Wenjian Yu
DOI: 10.1109/asp-dac66049.2026.11420561
Cited by: 0
References: 21

Fields of Study & Subjects

VLSI and FPGA Design Techniques Analog and Mixed-Signal Circuit Design VLSI and Analog Circuit Testing

Publication details

Journal / source
Asia and South Pacific Design Automation Conference (ASP-DAC)
Pages
660–666
Publication date
19 January 2026
Language
EN