SCION: A Comprehensive Simulation Framework for Charge-based In-Memory Computing for Rapid Evaluation of Hardware Non-Idealities and DNN Accuracy

Charge-based in-memory computing (IMC) has shown great potential in achieving higher computational robustness compared to current-based IMC. However, it suffers from its own non-idealities such as parasitic capacitive coupling. Accurately evaluating these effects requires time-intensive SPICE simulations, making it challenging to conduct cross-layer exploration. To overcome these limitations, we propose SCION, a PyTorch-based framework that rigorously models hardware non-idealities in charge-based IMC and integrates them directly with DNN inference for rapid accuracy evaluation. We show that SCION predicts the IMC output with more than 99% accuracy with respect to SPICE while offering four orders of magnitude speedup. We demonstrate the capability of our framework by analyzing an SRAM-based charge-IMC accelerator deploying ResNet-50 and ViT-small DNNs with CIFAR-100 dataset. We show how inter-column capacitive coupling leads to data-dependent non-idealities, severely impairing the inference accuracy. We also explore techniques to mitigate non-idealities using SCION. To that end, we propose alternate column enablement (ACE) to eliminate inter-column coupling. Our results show that compared to the baseline design and another non-ideality mitigation approach based on ground shielding, ACE achieves significant improvement in sense margin and near-software accuracy under nominal conditions. Further, compared to ground shielding, ACE exhibits a higher tolerance to analog-to-digital converter (ADC) noise and superior voltage scalability.