Boosting Scalability and Performance: Macro Placement for Flexible 3D-Stacked ML Accelerators

Machine learning (ML) accelerators increasingly demand architectural flexibility to support diverse workloads. While reconfigurable designs like Self-Adaptive Reconfigurable Arrays (SARA) improve adaptability, they suffer from physical design bottlenecks-particularly in memory-intensive settings where dense memory integration inflates area, wirelength, and energy consumption. To address these challenges, we propose a scalable multi-tier memory-on-logic (MoL) integration framework that co-optimizes macro placement and standard-cell layout for flexible ML accelerators. Our methodology combines architectural insights with subgradient-based convex optimization for global placement, followed by simulated annealing for overlap resolution and multi-tier partitioning. The proposed flow significantly improves area efficiency, routing congestion, and timing closure. Experimental results on ML workloads demonstrate up to 3.4 × runtime speedup, 4.4 × energy-delay product (EDP) improvement, and $2.3 \times$ chip area reduction compared to conventional two-tier MoL baselines, enabling practical deployment of high-performance, adaptive 3D ML accelerators.