C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization

View at publisher
Authors: Yichen Lu, Hao-Hsiang Hsiao, Rongjian LIANG, Wen-Hao Liu, Haoxing Ren
Cited by: 2
References: 36

Abstract

Despite achieving orders-of-magnitude runtime speedup, GPU-accelerated placers (GPU-Placers) still have extremely limited industrial adoption, largely due to the wide gaps in Power, Performance, and Area (PPA) metrics compared to those well-established CPU-centric commercial Physical Design (PD) tools. To overcome this issue, we introduce C3PO, the first commercial-quality, differentiable, multi-objective global placer that performs concurrent timing, routability, and wirelength optimization in a coherent manner with custom CUDA kernels. Particularly, we propose a convex-based framework that dynamically computes objective weights at each placement iteration by solving a quadratic problem, eliminating the need of manual parameter tuning. In the experiments, we rigorously validate C3PO with an industry-leading commercial PD tool and demonstrate that on 8 designs from TILOS [1] and IWLS [2] in ASAP 7nm [3], C3PO consistently outperforms the commercial tool by up to 16.7% in routed wirelength and 19.6% in switching power with complete full-flow validation.

Fields of Study & Subjects

Optical Network Technologies Advanced Optical Network Technologies VLSI and FPGA Design Techniques

Publication details

Journal / source
2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)
Publisher
IEEE
Pages
765–771
Publication date
19 January 2026