LMESN: A Leakage-Driven MOSFET Reservoir for Scalable and Ultra-Low-Power Temporal Inference

Edge-based temporal inference demands energy-efficient and scalable computing architectures, but existing analog reservoir computing models often face high energy costs and limited reconfigurability. We present LMESN, a leakage-current-driven, pulse-based reservoir computing architecture that exploits intrinsic threshold-voltage variation in standard CMOS to realize ultra-low-power stochastic dynamics. To overcome physical array size constraints, we propose a Shift-Multi-Mask (SMM) technique that emulates large virtual reservoirs through cyclic mask shifts, reducing update energy by over $100 \times$ and enabling single-cycle reconfiguration. To further boost task-level performance, we develop a hardware-software co-optimization framework that jointly tunes the ADC quantization range and reservoir mask structure via a discrete genetic algorithm. Post-layout simulations in 22 nm CMOS and evaluations on eight time-series datasets demonstrate up to 13.7% accuracy improvement and $5 \times$ variance reduction over unoptimized LMESN baselines. Compared to prior analog and neural network models, LMESN achieves 3–7 orders of magnitude lower energy consumption while delivering competitive or superior accuracy. Together, these innovations make LMESN a scalable, energy-efficient, and task-adaptive platform for edge temporal processing, setting a new direction in physical reservoir computing.