A Fast-Transient Dual-Domain Learning Digital LDO with Droop Timing Prediction and Proactive Timing-Aware Control for Adaptive Droop Mitigation

This paper presents a digital low-dropout regulator (DLDO) that employs a dual-domain learning scheme for enhanced droop mitigation and fast transient response. The proposed architecture incorporates a dual-domain learning self-adaptive compensation (DL- SAC) scheme, which performs real-time learning in both the voltage-current (V-I) and time domains. The V-I domain learning path identifies the optimal compensation current for a given droop magnitude, enabling rapid one-shot recovery, while the time-domain learning path predicts recurring droop intervals and proactively strengthens the droop detector for faster detection. A prototype was fabricated in a 28-nm CMOS process with a fully integrated 900 pF on-chip output capacitor. The prototype supports an input voltage VINof 0.8 to 1.2 V. Measurement results demonstrated a voltage droop of 120 mV and a droop settling time TS of 8.6 ns for an 82 mA load step with an on-chip test load, and a 59 mV droop with an 11.1 ns droop TS under a clock distribution emulation board integrating a clock buffer array at VINrange of 1.1 V and VOUTof 1.05 V. The proposed DLDO achieved droop reductions of 64 mV and 21.9 mV and TS improvements of 3.6 ns and 4.6 ns for the on-chip and emulation board condition, respectively.