THReaD: A 22.8 Mbps/node Two-dimensional Hierarchical Reconfigurable and Distributed Network for E-textiles with Fault Tolerance and Cooperative Power Management

To meet growing demands for scalability, modularity, and fault tolerance in e-textiles, this paper proposes THReaD: a Two-dimensional Hierarchical Reconfigurable and Distributed network-on-textiles (kNOTs) architecture using a 2-wire bi-Directional SPI-based (2DSPI) protocol to form yarn-connected meshes of direct-die-attached chiplets distributed at strategic locations on a textile. A System-on-Chip (SoC) chiplet (for computation or sensor interfacing) and a distributed power management unit (PMU) chiplet each contain dedicated 2DSPI blocks, enabling modular arrangements of both chiplet types for flexible and scalable 2D networks. The architecture supports hierarchical dimension-ordered routing and integrated fault tolerance mechanisms, achieving an effective bit rate of up to 22.8 Mbps per node, and PMU chiplets cooperate to scale 4.6× load current and 4.2× power reduction.