A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica Regulators Achieving 10.7mV Voltage Droop and 1.4ns Settling Time

This work presents a comprehensive scheme for mitigating all power-supply-induced jitter (PSIJ) sources along the write data strobe (WDQS) clock distribution network (CDN) in HBM interfaces. It comprises (1) a strobe-triggered digital LDO (ST-DLDO) for WDQS buffer and (2) local replica regulators (LRRs) for the following repeaters. The proposed scheme significantly suppresses PSIJ by reducing voltage droop (ΔVDROOP)with only a 10pF output capacitor per regulator and an IDLE-mode quiescent current (IQ) of 3.2μA. Moreover, it maintains a dropout voltage (VDO) of 100mV and at least-10dB power-supply rejection (PSR) across the entire frequency range. It supports a wide WDQS/2 frequency range from 0.4 to 3.5GHz. Fabricated in a 28nm CMOS process, the proposed architecture integrates a ST-DLDO occupying 0.005mm2and multiple LRRs of 0.003mm2each, achieving the best FoM among state-of-the-art small-ΔVDROOPLDOs.