Switching-Activity Reduction in BIST Through a Hybrid Test Pattern Generator by Using Gray-Code

2026 International Conference on Intelligent Processing, Hardware, Electronics, and Radio Systems (CIPHER) 2026

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Authors: Prachi Sawarn, Vrinda Gupta
DOI: 10.1109/cipher70417.2026.11523881
Cited by: 1
References: 16

Fields of Study & Subjects

VLSI and Analog Circuit Testing Ferroelectric and Negative Capacitance Devices Integrated Circuits and Semiconductor Failure Analysis

Publication details

Journal / source
2026 International Conference on Intelligent Processing, Hardware, Electronics, and Radio Systems (CIPHER)
Publisher
IEEE
Pages
1–5
Publication date
13 February 2026