High-Performance LDMOS with a Novel Stepped-Field Plate Optimized by Simulation

In this work, a novel stepped-field plate (SFP) LDMOS structure is proposed and optimized through Technology Computer-Aided Design (TCAD) simulations. The optimized device presents significantly enhanced performance along with a robust process window. The SFP-LDMOS incorporates a low-temperature oxide (LTO) deposition process to form a 100-nm-thick silicon oxide layer over the source-side edge of the conventional shallow trench isolation (STI) field plate. This configuration effectively modulates the electric field at the STI edge, leading to an improved breakdown voltage (BV). Meanwhile, by optimizing the length of the thick silicon oxide layer, its influence on the specific on-resistance (Ron,sp) is minimized in the on-state. Simulation results indicate that the SFP-LDMOS achieves a BV of 96.50 V and a Ron,spof 70.59 mΩ•mm2, outperforming conventional field-plate LDMOS structures.