HeteroSTA3D: A CPU-GPU Heterogeneous Static Timing Analysis Engine for 3D ICs

Three-dimensional integrated circuits (3D ICs) based on hybrid bonding have emerged as a key technology for sustaining performance scaling beyond the limits of conventional transistor shrinkage. However, the timing analysis of 3D ICs introduces challenges absent in two-dimensional (2D) designs, including combinatorial explosion in multi-corner analysis across heterogeneous technology nodes, inter-die parasitic modeling for hybrid bonding interconnects, and cross-die critical path extraction through a unified timing graph. No existing static timing analysis (STA) engine addresses these challenges natively. In this paper, we present HeteroSTA3D, the first CPU-GPU heterogeneous STA engine for 3D ICs. Targeting hybrid-bonding-based face-to-face two-die integration, HeteroSTA3D supports dual-die Liberty library management with independent process nodes, configurable bonding terminal parasitic modeling, multi-corner analysis across per-die PVT combinations, and end-to-end GPU-accelerated cross-die critical path search. HeteroSTA3D is released as an embeddable shared library with both industry-standard file formats and a zero-overhead flattened heterogeneous API for seamless integration into GPU-accelerated EDA flows. Experimental results show that GPU acceleration reduces runtime compared to CPU-only execution. A case study integrating HeteroSTA3D into a timing-driven 3D placement flow further demonstrates its effectiveness, achieving improved timing with affordable runtime overhead. HeteroSTA3D is freely available for academic use at https://heterosta3d.pkueda.org.cn/.