Embedded Tutorial Considerations on the Design of Resilient System-in-Package Based on On-Chip Lifecycle Management

This tutorial addresses the benefits one can take from deploying on-chip lifecycle management (OCLM) to design resilient Systems-in-Package (SiP). Such benefits are based on the massive deployment of on-chip cross-layer, collaborative sensors that are placed in strategic points of the chiplets and interposer, a data wrapper interface & management hub that is responsible to process and store the collected data from the sensors in a way to create an in-mission history of events, and on-chip analytics engine. The sensors can monitor from siliconlevel information (such as transistor aging, power-supply noise activity, electromigration, and transient faults in memory elements) up to system-level transactions in system bus, processor cores and memory IPs (e.g. task scheduling algorithm, and data and instructions fetched in memory). The sensors can be placed on dies on interposer. Furthermore, IEEE and IEC standards can be used to support data monitoring and collection processes. The analytics engine can be implemented based on simple/straightforward data structures such as Look-up Table (LUT) and Content-Addressable Memory (CAM), or be based on advanced Machine Learning/Artificial Intelligence (ML/AI) algorithms such as Dynamic Neural Network (DNN). The ultimate goal is to perform on-chip lifecycle management to trade, in-mission mode, power, performance, reliability and lifespan.