Backside Deep Trench Capacitors Integrated in Wafer-to-Wafer Hybrid Bonded 3D Stacks for PDN Impedance Suppression

Heterogeneous wafer-to-wafer hybrid bonding enables processor-near-memory stacking but also introduces high-frequency power integrity (PI) challenges. We demonstrate a hybrid-bonded 3D stack that integrates deep trench capacitors (DTCs) in the backside silicon after bonding. The DTCs are tied into the power network through TSVs and backside redistribution layers, providing a measured capacitance density of ~1200 nF/mm2without using active front-side area. Power delivery simulations show that placing these DTCs near power TSVs suppresses supply impedance above 1.6 GHz and improves noise margin in multi-wafer processor–memory stacks.