Analysis of Parasitic Series Resistance Effect in Gate-All-Around FETs by a Modified Alpha-Power Law Model

A new methodology to analysis parasitic series resistance (Rpr) for gate-all-around FET (GAAFET) is proposed. The α power law model based on the drain current is modified to an implicit function, considering the loss of gate voltage by IdsRprdrop. A modified α power model enables a simple Rprextraction strategy from experimental Ids–Vgscharacteristic of GAAFETs obtained in both linear and saturation regions. As a result, it is clearly found that reduction in Rpris achieved by using in-situ heavily P-doped epitaxial silicon (Si:P) for GAAFET, compared to planer-FETs by ion implantation followed by activation annealing. Our methodology is useful to analyze the critical resistance parameter for highly scaled three-dimensional devices.