High-Density Dual-Bit Charge Trapping Flash Memory: Design, Process Optimization, and Performance Evaluation

A high-density NOR array utilizing dual-bit charge trapping flash (CTF) technology is proposed, integrating a select gate structure and bit-line sharing architecture to achieve a compact cell size of 0.03 µm2/bit with Quad-Bit Cells (QBC) storage ability. Through advanced process optimization, the array demonstrates >98% yield, superior device uniformity, and narrow parameter distributions, including threshold voltage (VTH) and maximum transconductance (gm). The design ensures robust crosstalk immunity and high reliability, enabling efficient multi-level cell operation for next-generation nonvolatile memory applications.