Pulse: Fine-Grained Hierarchical Hashing Index for Disaggregated Memory

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Authors: Guofeng Deng, Zixiang Yu, Zhirong Shen, Qiangsheng Su, Zhinan Cheng, Jiwu Shu
Cited by: 0
References: 38

Abstract

By decoupling compute and memory resources into independent pools that are provisioned and managed separately, disaggregated memory (DM) is promising to break the scaling constraints for memory systems and improve resource utilization. However, it also comes with a new challenge to design a high-performance hashing index to manage the vast memory pool with weak computing power. In this paper, we reconsider this problem and find that existing hashing indexes for DM still experience two fundamental yet unresolved limitations: (i) amplifying traffic under high insertion concurrency, and (ii) introducing significantly high insertion latency, stemming mainly from the directory synchronization and item relocation in resizing process. We resolve the above limitations by designing Pulse, a finegrained hierarchical hashing index for DM. Pulse comprises the following three design primitives. It proposes a multi-level index structure, which breaks the conventional flat directory into multiple sub-directories that are organized hierarchically, achieving fine-grained directory synchronization. Pulse also maintains a small portion of hashed keys in the memory pool, which aids in item relocation during resizing, thereby reducing resizing traffic and promising system stability. Pulse finally exploits operation parallelism by tailoring the doorbell batching mechanism with selective signaling. We conduct extensive experiments using a variety of benchmarks, showing that Pulse can improve$3.46 \times$of the throughput and reduce 76.3% of the tail latency compared to state-of-the-art hashing indexes.

Fields of Study & Subjects

Parallel Computing and Optimization Techniques Advanced Database Systems and Queries Network Packet Processing and Optimization

Publication details

Journal / source
IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Pages
1–14
Publication date
31 January 2026
Language
EN