A Double-Node-Upset Self-Recoverable Latch with Soft Error Tolerance to Soft Errors Around Clock Edges

The continuous scaling of semiconductor technology, with smaller device dimensions and lower supply voltages, has significantly increased the susceptibility of circuits to soft errors. In particular, soft errors injected at input nodes around clock edges pose serious risks of erroneous sampling, which most existing hardened latch designs do not address. This paper presents a novel latch architecture that achieves complete selfrecovery from double-node upsets (DNUs) while also providing robustness against soft errors occurring at input nodes around clock transitions. The proposed design employs delay elements (DEs) to introduce temporal redundancy, enabling effective masking of transient faults. Simulation results based on a 1 5 nm FinFET process confirm that the latch can fully recover from single-node and double-node upsets and reliably tolerate soft errors around clock edges. Although the proposed DE offers large delay capability, it incurs considerable power overhead. Comparative analysis demonstrates that the latch achieves enhanced fault tolerance compared with state-of-the-art designs, while highlighting power as the primary limitation, suggesting the potential for further optimization.