Academic Open-Source EDA Tool for CMOS Full-Custom Chip Layout and Physical Verification

This paper presents a free and open-source electronic design automation (EDA) tool based on KLayout for CMOS full-custom chip layout and physical verification in large-scale classroom teaching. The framework incorporates custom mask layers, design rule check (DRC), and layout versus schematic (LVS) functions, enabling students to complete mixed-signal integrated circuit projects. A virtual 180 nm CMOS process is employed in a final project to design a 4-bit full-adder, demonstrating both software functionality and its suitability for educational use. The tool supports Windows, macOS, and Linux platforms, allowing students to readily access it in computer laboratories and on personal devices.