Optimization of Dynamic Comparator Architectures for High-Speed 4-Bit Flash ADCs in Deep-Submicron CMOS

This paper presents a performance evaluation of 4-bit Flash Analog-to-Digital Converter (ADC) employing four distinct dynamic comparator architectures implemented in three different CMOS processes, 45nm, 65nm and 90nm. The impact of various comparator architectures has been thoroughly analysed in terms of power consumption, delay, Effective Number of Bits (ENOB), Signal-to-Noise Ratio (SNR), Signal-to-Noise and Distortion Ratio (SINAD), Spurious-Free Dynamic Range (SFDR), and Figure of Merit (FOM) in order to achieve the goals of this work. With a 1 V power supply and a 1 V peak-to-peak sinusoidal input signal, the ADC architecture is fully built, simulated, and assessed in Cadence Virtuoso using Spectre under the same supply conditions. The effect of dynamic comparator designs on flash ADC architecture and overall efficiency is assessed by comparing key performance parameters, including as conversion delay, power dissipation, SNDR, and ENOB. In comparison to traditional designs, the suggested comparator achieves lower power consumption and moderate energy efficiency. These results imply that the overall performance of low-resolution, high-speed Flash ADCs can be greatly enhanced by optimized dynamic comparator choices.