Analysis of p-GaN-Gate HEMTs: Impact of Gate Length and Gate-to-Drain Spacing on Device Performance and Characteristics

A study has been performed on p-GaN AlGaN/GaN High Electron Mobility Transistors (HEMTs) to improve device performance and electrical properties with Silvaco TCAD modeling. The impact of essential geometric parameters, such as gate length (Lg) and gate-to-drain spacing (Lgd), on threshold voltage, output characteristics, drain current, and breakdown voltage is systematically analyzed using the program. Results indicate that, maximum drain current (Id₍max₎) drops from 0.873 A/mm to 0.458 A/mm as the gate length (Lg) grows from 1.4 μm to 6 μm. The breakdown voltage increases from 25 V to 830 V when the gate-to-drain spacing (Lgd) is increased from 1 μm to 5 μm at a given gate length of 1.4 μm. Shorter Lgvalues, on the other hand, increase short-channel effects and lower the threshold voltage. To achieve optimal device performance, need to keep the gate length (Lg) between 1-3 μm, and use a large gate-to-drain spacing (Lgd) of several micrometers. Excessive Lgdreduction could exacerbate short-channel effects and impair performance. Therefore, creating dependable and high-performance p-GaN HEMTs requires finding the optimal trade-off between high current capability, threshold voltage stability, and breakdown voltage.