Design and Analysis of Reconfigurable FP16INT8 Dual-Mode Multiplier on FPGA

This work presents a dual-mode multiplier capable of performing multiplications in both $\mathbf{1 6}$-bit floatingpoint (FP16) and 8-bit integer (INT8) formats. The proposed multiplier integrates the conventionally separated FP16 significand multiplier and INT8 multiplier into a unified architecture to enhance resource utilization efficiency. By reconfiguring the data path of the partial product (PP) reduction stage, the proposed design reuses a single FP16 significand multiplier to process two pairs of INT8 multiplications, thereby achieving $2 \times$ throughput improvement. The proposed dual-mode multiplier was implemented and verified on the ZCU104 FPGA Evaluation board, demonstrating a $30.56 \%$ reduction in resource utilization compared to separate implementations of FP16 and INT8 multipliers.