A 0.61-pJ/Bit 48-Gb/s PAM-4 Transceiver with a Time-Domain Decoder reducing DFE Feedback path for Low Power Memory Interface in 28-nm CMOS

This paper presents a $\mathbf{4 8 - G b} \boldsymbol{/} \mathbf{s}$ four-level pulse-amplitude modulation (PAM-4) transceiver for next-generation low-power memory interfaces implemented in $\mathbf{2 8}-\mathbf{n m}$ CMOS technology. To achieve low power consumption, a time-domain comparator is proposed in the receiver. The proposed time-domain decoder divides the comparator output into three levels by setting the reference voltage to the middle data level. This reduces the number of comparators to two-thirds of conventional PAM-4 receiver. Furthermore, the increased comparator input voltage swing allows for a reduction in the TX driver supply voltage (VDDQ), saving area and improving power efficiency. The transceiver employs a 2-tap feed-forward equalizer (FFE) and a 1-tap decision feedback equalizer (DFE) to compensate for inter-symbol interference (ISI) in a channel with $-\mathbf{8} \mathbf{~ d B}$ loss at Nyquist frequency. The prototype achieves a $48-\mathrm{Gb} / \mathrm{s}$ data rate with an energy efficiency of $0.61 \mathrm{pJ} / \mathrm{bit}$, demonstrating its suitability for future low-power, high-speed memory interfaces.