Energy Efficient 16 Transistor Full Adder Circuit

A speedy increase is been found with-inside the vicinity of Integrated Circuits (IC) technology. All the ICs are to be designed in an optimized manner so they meet all of the necessities of being faster, occupying much less vicinity and decreased energy consumption. Adder is the maximum essential constructing block in VLSI, microprocessors and digital signal processors. So, Energy efficient 16 transistor full adder circuit is the proposed work, with one of a kind strategy to lessen the delay time and energy consumption. The important goal of this paper for the full adder is feeding not only low power and high speed but additionally with driving prospect. The different logics have been compared with the results to show which is the appropriate one for the low delay time and has low power consumption. The proposed energy efficient circuit is designed using optimized logic with Cadence virtuoso 90 nm technology node and shows 35% power reduction and compared with the traditional method.