A Scalable 64-Bit Hybrid Multiplier Combining Vedic Arithmetic and Wallace Tree Compression

Innovative developments in the fields of high-performance computing, signal-processing platforms, and autonomous embedded systems have jerked the demand for arithmetic units to be ultra-fast and power-efficient. Multipliers, the most computation-heavy modules in each data path, thus form the major specifications for throughput, latency, and silicon footprint of modern VLSI systems. This innovation has resulted in an optimized 64-bit Hybrid Vedic-Wallace Tree Multiplier synthesizing the computational parallelism of Urdhva tiryagbhyam and efficiency reduction in operand with the Wallace Tree architecture. This hybrid model is characterized by Vedic partial-product generation combined with logarithmic depth compression stages and a high-performance Kogge-Stone final adder. In-depth evaluation using Verilog HDL confirms that the architecture surpasses all conventional architectures-those based on Wallace, UT-based Vedic and Nikhilam in propagation delay, structural regularity and resource efficiency. Including over 4.6 ns of critical-path delay confirms the necessary merits to qualify the design as highly attractive for next-generation DSP accelerators, cryptographic processors, low-latency embedded architectures, and high-frequency FPGA/ASIC implementations. Future extensions will comprise pipelined hybrids, power-aware adaptive multiplier cores, and quantum-ready reversible architectures.