AI-Assisted Low-Power VLSI Synthesis using Reinforcement Learning for Gate-Level Power Optimization

This paper presents a constrained actor-critic framework that combines an attention-pooled graph neural network encoder with a calibrated surrogate ensemble to drive low-power gate-level VLSI synthesis. The approach flattens RTL to annotated gate netlists, uses a compact message-passing GNN to produce per-gate embeddings and a pooled global state, and issues hybrid actions (discrete local edits plus continuous sizing) through an actor-critic policy. Fast surrogate GNN regressors provide inner-loop estimates for power and timing with ensemble-based uncertainty; periodic full-tool calibration (OpenSTA/FastPower) and a safety filter with a Lagrangian controller enforce timing budgets and maintain surrogate fidelity. Evaluation across small, medium, and large benchmarks shows median power savings of 10–18% relative to a baseline heuristic, typical area impact below 2%, and an effective training/runtime multiplier of about 1.8× (full-STA training rises to ~4.5× without surrogates). Calibration reduced surrogate MSE for power from ~0.024 to ~0.006 and for timing from ~0.031 to ~0.008, lowering high-uncertainty episodes from ~12% to ~3%. Ablation studies confirm the value of attention pooling and surrogate acceleration. The method offers a practical, reproducible path to integrate learning-based low-power optimization into existing EDA flows.