Design and Implementation of a Logarithmic Floating-Point Multiplier Using a Brent–Kung Adder for FPGA-Based Error-Tolerant Applications

In this paper, the design and implementation of a Logarithmic Floating-Point Multiplier (LFPM) with a Brent-Kung Adder (BKA) is described to support FPGA-based applications which are error-tolerant. The image processing, neural network accelerators and signal processing (among other tasks) are some of the high-performance computing systems that heavily depend on floating-point multiplication; speed, hardware efficiency and energy consumption are primary design factors in such systems. The input floatingpoint operands are sign, exponent, and mantissa fields in the proposed architecture. An XOR operation is used to compute the sign of the product whereas exponent computation is done with a BrentKung parallel prefix adder to provide effective propagation of carries. Multiplication of the mantissa numbers is simplified with the help of logarithmic approximation, which is then converted to the anti-logarithmic number and then normalized and packed with the final result. There are also special cases like zero, infinity and NaN treated in accordance to the requirements of floating-point arithmetic. It is designed in Verilog HDL and compiled and executed on the Xilinx Vivado on the Kintex-7 FPGA device xc7k70tfbv676-1. It has been experimentally observed that the current LFPM architecture uses 75 Slice LUTs (0.18 %) with the overall delay of 20.495 ns whereas the proposed architecture uses 105 Slice LUTs (0.26 %) with the overall delay of 20.8 ns. The proposed design is somewhat more demanding in the amount of logic resources, but it offers a superior arithmetic structure whose scalability is more likely and its applicability to error-tolerant systems. The offered LFPM that combines with BrentKung Adder is thus a prospective remedy of effective FPGA-based arithmetic real-time and energy efficient computing tasks.