Energy-Efficient Peres—Feynman Reversible 8-Bit Polar Encoder and Decoder on Xilinx Artix-7 FPGA for Low-Power and Quantum Applications

Using hybrid Peres and Feynman reversible gates, this study provides an energy-efficient reversible 8-bit Polar encoder and decoder that is built on an Xilinx Artix-7 FPGA. To ensure full logical reversibility throughout all Polar transform phases, the proposed design replaces the irreversible logic gates used in the current architecture with hybrid Peres and Feynman reversible gate architectures. Utilizing the Xilinx Vivado simulation and synthesis tool, the design and functional verification are completed. Results from FPGA implementation show notable gains over the traditional method. Approximately$\mathbf{1 2. 8 \%}$less static power, 22.9% less dynamic power, 22.7% less on-chip power, 42.8% less LUT usage, and 44.4% less flip-flops are used in the encoder. The decoder also sees a reduction in static power of 13.1%, dynamic power of 14.7%, on-chip power of 14.7%, LUT usage of 33.3%, and flip-flops of 37.5%. These outcomes demonstrate that the proposed design offers a compact, low-power, and FPGA-efficient solution suitable for applications involving reversible computation and wireless communication.