Descriptor: Asynchronous Circuit Logic Dataset (ACLD)

This paper presents the Asynchronous Circuit Logic Dataset (ACLD), which comprises 4 pipeline structures and 26 asynchronous design templates based on 6 data channel configurations, containing 120 asynchronous circuit logic designs. Each logic design is stored in an individual repository that includes easily accessible description files (.json), transistor-level circuit description files (.sp), and associated testbench files (.sp) for functional simulation. In contrast to existing resources restricted to isolated design templates, the ACLD establishes a unified platform with standardized performance metrics, including delay, switching energy, and static power. This facilitates consistent benchmarking of asynchronous circuit logic across diverse pipeline structures for both academic and industrial applications.