An Efficient Switch-Capacitor Charge Pump for Enhanced PLL Performance in 5G Transceivers

The fifth generation of cellular technology, widely known as 5G, goals to upgrade the wireless communication technology by adopting a broad spectrum at higher frequencies for numerous emerging applications, including augmented reality, autonomous vehicles, and the Internet of Things (IoT). Charge Pump (CP) is one of the critical components of 5G transceiver’s phase-locked loops (PLLs). This CP, along with the phase frequency detector and loop filter, plays a pivotal role in adjusting the voltage-controlled oscillator (VCO) frequency based on phase mismatch error. The CP module is mostly responsible for PLL locking by mitigating the current mismatch. To make PLL locking faster, researchers have reported various types of solutions, often resulting in bulky and power-intensive implementations. In this study, a switch-capacitor-based CP design is proposed using 90 nm complementary metal oxide semiconductor (CMOS) technology in Cadence Virtuoso software. The designed CP achieves remarkably low power consumption of only 17.38 μW, with an impressively low current mismatch of 0.034%. These findings demonstrate the prospect of the proposed CMOS CP design to enhance PLL performance, offering a promising solution for low-power, high-performance 5G transceiver applications.