Low-Latency EDMA Framework for AI-Based DSP SoCs in Multimedia Real-Time Systems

Real-time multimedia systems demand highspeed data transfer with minimal latency to support continuous video, audio, and image processing. Conventional CPU-based memory transfer introduces performance bottlenecks due to processor intervention in every transaction. To overcome this, the proposed work presents a low-latency Enhanced Direct Memory Access (EDMA) framework for AI-based DSP System-on-Chip (SoC) applications. The architecture automates memory transfers through dedicated hardware logic, thereby reducing CPU load and accelerating data movement. Both CPU and EDMA modules were implemented in RTL and synthesized using Cadence Genus in 45 nm technology, with functional verification carried out in Cadence SimVision. Results show that the EDMA design achieves lower cycle counts, efficient area utilization, and reduced power consumption compared to the CPU-only approach. Proposed EDMA achieves faster and more efficient data handling while reducing processor workload with total power consumption of 62.41nW and a chip area of 950.666$\mu \mathrm{m}^{2}$compared to the results reported in the literature. The framework demonstrates its potential for integration into highthroughput, real-time multimedia SoCs, ensuring faster data handling with minimal latency.