Energy-Efficient and High-Speed Shift Registers for Sustainable VLSI Using Tri-Mode Multi-Threshold CMOS

In this work, an optimized shift register architecture leveraging the Tri-Mode (Power-Gated) Multi-Threshold CMOS (MTCMOS) technique is proposed to reduce power consumption and delay while maintaining circuit stability. The design optimizes D Flip-Flops (DFFs) and implements a 3-bit shift register using these optimized components. The proposed circuits have been simulated and implemented on a 180nm technology node using Electronic Design Automation (EDA) tools, demonstrating significant improvements over conventional designs. The Tri-Mode MTCMOS technique achieves 55.31 % power reduction and 28.92% delay reduction in DFFs. For Serial-In Serial-Out (SISO) shift registers, power and delay reductions of 51.38% and 23.60% are observed, while Parallel-In Parallel-Out (PIPO) shift registers achieve 53.69% power reduction and 82.54% delay reduction. The proposed low-power and high-speed shift register design contributes to the development of energy-efficient VLSI circuits, which are crucial for next-generation sustainable electronic systems. By effectively minimizing leakage power and enhancing circuit stability, this approach supports green computing initiatives and advances the field of sustainable, power-aware circuit design.