Design of an Optimized 8-Bit Flash ADC using a Double-Tail Comparator in 45nm CMOS Process

This study focuses on the design and performance analysis of an 8-bit Flash Analog-to-Digital Converter (ADC) that utilizes Threshold Inverter Quantization (TIQ) along with an enhanced double-tail (DT) comparator architecture. The proposed architecture demonstrates enhanced speed and power efficiency over conventional implementations. At the comparator level, the conventional DT comparator exhibits a power consumption of$14.35 \mu \mathrm{w}$, a delay of 2.065 ns, and a power–delay product (PDP) of 29.63 fJ. In comparison, the proposed DT comparator reduces power to$7.12 \mu \mathrm{W}$with a shorter delay of$\mathbf{1. 7 4 ~ n s}$, resulting in a PDP of$\mathbf{1 2. 3 8 ~ f J}$. Furthermore, the maximum operating frequency (f_max =$\mathbf{1} / \mathbf{2 T}$_dp) improves from$\mathbf{3 4. 8 4 ~ M H z}$to$\mathbf{7 0. 2 2 ~ M H z}$. The complete Flash ADC achieves a total power consumption of 21$\mu \mathrm{W}$, thereby making it a promising solution for low-power, high-speed applications in portable and battery-powered systems.