On-Chip AI Security Engine for Post-Quantum IoT
Abstract
The runaway proliferation of Internet of Things (IoT) devices, coupled with the looming specter of quantum computing, necessitates security hardware that is not only quantum-resilient but also resource-frugal. The present paper outlines a single on-chip AI security processor that integrates post-quantum cryptography (PQC) acceleration and real-time anomaly detection into one VLSI-optimized package. The proposed architecture combines a RISC-V core with instruction set extension custom instructions, a CRYSTALS-Kyber PQC core, a Dilithium authentication module, and an INT8-quantized 1D-CNN accelerator, all interfaced through dual-port SRAM to enable concurrent data access. The architecture liberates the latency and energy expense of sequential$\text{AI}+\text{PQC}$pipelines by enabling parallel execution and shared memory utilization. FPGA prototyping on a Xilinx Kintex-7 platform reduces the average latency by 31.1 % and improves the energy efficiency by 31.0 % compared to sequential implementations, while maintaining 96.0% intrusion detection and 128-bit post-quantum security strength. The results verify the applicability of using integrated AI-PQC security engines in constrained IoT applications without performance or cryptographic strength degradation.
Fields of Study & Subjects
Physical Unclonable Functions (PUFs) and Hardware Security
Cryptographic Implementations and Security
Chaos-based Image/Signal Encryption
Publication details
- Journal / source
- 2026 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE)
- Publisher
- IEEE
- Pages
- 1–6
- Publication date
- 22 January 2026