Modular Top Level Architecture Synthesis and Signal Routing in a 32-Bit RISC Processor

The RISC-V instruction set architecture (ISA) is gaining wide adoption in domains such as IoT, embedded systems, and academic research due to its open-source, modular, and flexible design. A CPU core that is both efficient and easily verified is a basic prerequisite for such applications. In this work, we present the design and implementation of a Verilog HDL-based 32-bit single-cycle RISC-V processor that supports the RV32I instruction set. The processor integrates an Arithmetic Logic Unit (ALU), Register File, Control Unit, and Memory into a structured and modular datapath. Simulation and functional verification were performed using Eda Playground, where the correctness of instruction execution was confirmed through waveform analysis. The result of ALU operations is governed by the opcode and operands, where arithmetic operations (e.g., addition) perform A+B, logical operations (e.g., AND) perform$\mathrm{A} \wedge \mathrm{B}$, and memory instructions handle load/store between registers and memory. Status flags such as zero, carry, negative, and overflow are updated accordingly. The proposed design demonstrates improved efficiency through optimized control logic and reduced critical path delay, ensuring faster instruction execution in single-cycle operation. This processor serves as a foundational model for future enhancements such as pipelined or low-power architectures aimed at increasing performance and energy efficiency. The proposed modular top-level architectural synthesis approach improves scalability, verification simplicity, and enables seamless extension toward pipelined RISC-V architectures.