A Decoder-Based CNTFET Ternary Half-Adder Design

Multi-valued logic (MVL) has been widely investigated as an alternative to conventional binary logic due to its ability to represent information more efficiently and reduce interconnection complexity. The design choices adopted in this work were guided primarily by circuit simplicity and practical implementability rather than theoretical optimality. This work proposes a ternary half-adder (THA) circuit which implements a previous proposed energy efficient ternary decoder (TDecoder) using carbon nanotube field-effect transistors (CNTFETs). The proposed THA reuses the outputs of the decoder as intermediate signals to generate the SUM and CARRY. Simulations results via HSPICE show that the proposed THA achieves up to 76.8% compared to a traditional THA.