A Pipelined NoC-Based Membrane Shortcut SNN Architecture for Low-Latency Spike Sorting

2026 IEEE International Symposium on Circuits and Systems (ISCAS) 2026

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Authors: Jingsong Zhang, Y C Zhu, Fangduo Zhu, Chenyang Li, Siyuan Ouyang, Jinhao Liang, J Y Chen, Xumeng Zhang, Qi Liu
DOI: 10.1109/iscas66217.2026.11562720
Cited by: 1
References: 24

Fields of Study & Subjects

Interconnection Networks and Systems Network Packet Processing and Optimization Advanced Memory and Neural Computing

Publication details

Journal / source
2026 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher
IEEE
Pages
3246–3250
Publication date
24 May 2026