Effective Capacitance Modeling Using Graph Neural Networks

Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the design, but at the same time, placement and routing efficiency depend on the final timing performance. VLSI design flows can benefit from timing-related prediction to better perform the earlier stages of the design flow. Effective capacitance is an essential input for gate delay calculation, and finding exact values requires routing or routing estimates. In this work, we propose the first GNN-based post-layout effective capacitance modeling method, GNN- $C_{\text {eff }}$, that achieves significant speed gains due to GPU parallelization while also providing better accuracy than current heuristics. GNN-$C_{\text {eff }}$ parallelization achieves 929x speedup on real-life benchmarks over the state-of-the-art method run serially.