Scalable Security Monitoring on Chiplet-Based Systems

To protect emerging AI chiplet-based systems against various attacks, a promising approach is to deploy a distributed network of on-package security modules to monitor individual chiplets. These monitors can be implemented either as active elements integrated within the substrate or as dedicated security helper chiplets. Connected through a secure intrapackage network, these components continuously observe communication among regular chiplets (e.g., CPU, GPU, accelerators) and memory. Additionally, the security chiplets can provide ondemand security services, such as trusted execution environments (TEE) and cryptographic operations, to the functional chiplets. To explore the feasibility, usefulness, and trade-offs of such a design, we study the cost, power, and performance implications of using this model by developing a new framework. Our analysis highlights the cost tradeoffs across different design strategies.