A 0.65-to-1V-V DD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS
Abstract
This paper presents a 0.65-to-$1 \mathrm{V}, 10.5$-to-11.85 GHz wide-$\mathrm{V}_{\text{DD}}$-range (WV) fractional-N sampling PLL. The QE-reduction WV SPD, high-linearity 2-stage DTC, and DCC-aided QE dithering method are proposed to address the issue of poor phase noise at low$\mathrm{V}_{\text{DD}}$, reliability at regular$\mathrm{V}_{\text{DD}}$, nonlinearity, and convergence issues at small fractional FCWs. The 40 nm prototype achieves 71.47fs jitter, −251.8 dB FoM, and$
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Low-power high-performance VLSI design
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 218–220
- Publication date
- 15 February 2026