37.2 A 47.0Tb/s/mm 112Gb/s/pin PAM4 Single-Ended Transceiver Featuring 4-Aggressor Crosstalk Cancellation and Supply-Noise Tolerance for Short-Reach Memory Interfaces

Qian Liu; Yiheng Hui; Yuanlin Nong; He Ma; Yan Xu; Hao Hu; Junwei Zhu; Quan Wang; Lei Wang; Li Du; Yuan Du

doi:10.1109/isscc49663.2026.11408977

37.2 A 47.0Tb/s/mm 112Gb/s/pin PAM4 Single-Ended Transceiver Featuring 4-Aggressor Crosstalk Cancellation and Supply-Noise Tolerance for Short-Reach Memory Interfaces

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Qian Liu, Yiheng Hui, Yuanlin Nong, He Ma, Yan Xu, Hao Hu, Junwei Zhu, Quan Wang, Lei Wang, Li Du, Yuan Du

DOI: 10.1109/isscc49663.2026.11408977

Cited by: 0

References: 9

Abstract

This paper presents a five-lane 112Gb/s/pin PAM4 single-ended transceiver in 28nm CMOS for high-density short-reach memory interfaces. Low-power triple-equalization, 4-aggressor shape-fitting crosstalk cancellation and supply-noise-tolerant clock distribution networks are involved to improve the signal integrity. The design demonstrates robust performance against severe crosstalk and supply noise, achieving an energy efficiency of 0.52pJ/b and an edge density of 47.0Tb/s/mm.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design Low-power high-performance VLSI design

Publication details

Journal / source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages: 626–628
Publication date: 15 February 2026
Language: EN

References 9