A 144mW 161Mpixels/s Tensor Display Processor for 3D Virtual Reality

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Ching-Yen Lee, Yueh-Feng Tsai, Ying‐Sheng Lin, Chia‐Hsiang Yang
DOI: 10.1109/isscc49663.2026.11408983
Cited by: 0
References: 7

Abstract

This work presents a 3D display processor that converts the focal stack to tensor display. Algorithm-architecture co-optimization is applied to reduce the computational complexity and hardware complexity. It achieves the maximum throughput of 161 Mpixels/s (equivalent to 87 fps at HD resolution) at a clock frequency of 200 MHz, with normalized energy consumption of$0.9 \text{nJ} /$pixel, and a PSNR of 23.7 to 24.8 dB,

Fields of Study & Subjects

Advanced Optical Imaging Technologies Advanced Vision and Imaging Video Coding and Compression Technologies

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
414–416
Publication date
15 February 2026
Language
EN