A 1.6-to-3.8GHz Reconfigurable FMCW Radar SoC with 81.5% Relative-Bandwidth PLL for Real-Time Life Detection in Disaster Response

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Renjie Fu, Linxu Shi, Fanxun Cai, Yunqi Yang, Hao Lei, Zhigang Fu, Yilin Xu, Pengcheng Wang, Ziyang Li, Shixuan Wang, Junkai Jiao, Dingqi Liang
+9 more Lianbo Wu, Guangzhong Zhang, Naike Du, Zijie Wang, Yucong Gu, Xiuzhu Ye, Xiao Fang, Weisheng Zhao, Hui Zhang
DOI: 10.1109/isscc49663.2026.11408988
Cited by: 1
References: 24

Abstract

A 1.6-to-3.8GHz FMCW radar SoC for real-time non-line-of-sight life detection is implemented in 40nm CMOS. An 81.5% BW ring-VCO PLL with DTC achieves 29.6kHz frequency error and 0.78-to-400MHz/µs chirp slopes. The TX integrates a 13.43dBm PA, while the RXRF features 8.1dB NF, baseband chain with 100dB-rejection SC-HPF at 1kHz and CT Δ-∑ ADC. A RISC-V core with FPU/VPU enables DSP, detecting people behind 6 walls and vital signs behind 2, occupying 7.65mm2and consuming 0.395W.

Fields of Study & Subjects

Radio Frequency Integrated Circuit Design Full-Duplex Wireless Communications Non-Invasive Vital Sign Monitoring

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
582–584
Publication date
15 February 2026