A 2×2 10GS/s TTD BF Receiver Utilizing Charge-Based Summation with 10.5GHz Bandwidth and SNDR/SFDR with 49.5dB/57.5dBc in 22nm CMOS

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

View at publisher
Authors: Enne Wittenhagen, Dominik Wilding, Patrick James Artz, Sebastian Linnhoff, Philipp Scholz, Friedel Gerfers
DOI: 10.1109/isscc49663.2026.11408989
Cited by: 0
References: 6

Abstract

This work presents an ultra-compact$10 \text{GS} / \mathrm{s}$sampled beamforming (BF) receiver front-end (FE) for a$2 \times 2$antenna array, enabling both azimuth and elevation steering in 22 nm FDSOI CMOS. The$4 \times$time-interleaved FE features a 200 ps range/14.3ps LSB true-time-delay employing a TaH-based BF with passive charge-based summation with 10.5 GHz signal bandwidth, eliminating power-hungry summing amplifiers. The FE receiver achieves an SFDR/SNDR$>57.5 \text{dBc} / 49.5 \text{dB}$with only$52 \text{mW} /$channel and a Schreier FOM of 153 dB.

Fields of Study & Subjects

Radio Frequency Integrated Circuit Design Analog and Mixed-Signal Circuit Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
104–106
Publication date
15 February 2026
Language
EN