A Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Chang-Hyo Yu, Jaewan Bae, Jinseok Kim, Hongyun Kim, Wongyu Shin, Jae-Sung Yoon, Young-Jae Jin, Jungju Oh, Jaebong Lee, Eunseo Kim, Miock Chi, Sungpill Choi
+33 more Donghan Kim, Hyunje Jo, Hyunho Kim, Hyungseok Heo, Hyunsung Kim, Seung-Goo Kim, Myunghoon Choi, Sangeun Je, J. Van Ham, Juyeong Yoon, Yashael Faith Arthanto, Sung-Il Bae, Sanggyu Park, Joungwoo Lee, Heeyoung Chae, Kiljun Ryu, Yongjik Kim, Jin-O Seo, Nara Cho, Taeyoung Jeon, Gukchae Ahn, Myoungoh Ki, Junkyeong Choi, Seungcheol Baek, Daehoon Kim, JuHwan Kim, SungMoon Kang, Sieon Son, Minseo Kim, Yeounghwan Choe, Younggeun Lee, Sunghyun Park, Jinwook Oh
DOI: 10.1109/isscc49663.2026.11409003
Cited by: 2
References: 1

Abstract

A 4nm-based quad-chiplet with an advanced packaged LLM accelerator achieving 56.8TPS on LLaMA v3.3 70B with single-batch 2k/2k input/output sequences. The architecture combines chiplet-based design, low-latency die-to-die interfaces, unified mixed-precision compute, holistic synchronization, and HBM3E with advanced power schemes to sustain bandwidth, capacity and thermal stability. The SoC integrates four NPU chiplets, four HBM3E modules, and four ISCs for stable power delivery.

Fields of Study & Subjects

Low-power high-performance VLSI design Embedded Systems Design Techniques VLSI and FPGA Design Techniques

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
44–46
Publication date
15 February 2026