25.6 A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Cankun Zhao, Hanyue Shui, Bohan Yang, Wenping Zhu, Yuluan Cao, Hou Zhang, Yuqi Liu, Xiangdong Han, Shuying Yin, Weinan Chen, Hanning Wang, Jie Yang
+3 more Min Zhu, Aoyang Zhang, Leibo Liu
DOI: 10.1109/isscc49663.2026.11409007
Cited by: 1
References: 23

Abstract

This 0.046 mm2SHA-3 engine demonstrates overheads of only 17% area, 27% energy, and 0% latency while achieving provable glitch- and transition-robust security (power/EM TVLA MTD$>100 \mathrm{M}$). Glitch-free DPL reduces masked states by$3 \times$, resulting in a$72,950 \mu \mathrm{m}^{2}$register area reduction and lower logic energy. LMDPL refresh preserves secure asymmetric-share mapping. Masked transitions enable partial replacement of DPL with SRL, saving$50,852 \mu \mathrm{m}^{2}$in registers, precharge gates, and multiplexers.

Fields of Study & Subjects

Electromagnetic Compatibility and Noise Suppression Wireless Power Transfer Systems Pulsed Power Technology Applications

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
434–436
Publication date
15 February 2026