A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces
Abstract
This work presents a 0.87pJ/b, 17Gb/s/pin parallel receiver with local DQS recovery and a dual-DQS tree for reduced clock power and mitigated power supply-induced jitter (PSJJ). The local DQS recovery time-multiplexes a CML and an inverter tree$(^1/_{8}:^{7}/_8)$, enabling a hidden lock to the CML tree and subsequently generating a PSIJ-filtered DOS from the inverter tree with low power consumption. Fabricated in 40nm CMOS, it achieves$< 10^{-12}$BER under$100\text{mV}_{\mathrm{P}\mathrm{P}}$supply noise, while reducing clocking power by 70%.
Fields of Study & Subjects
Low-power high-performance VLSI design
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 638–640
- Publication date
- 15 February 2026
- Language
- EN